Free Pure Storage FlashArray-Implementation-Specialist Practice Exam with Questions & Answers | Set: 7

The FlashArray//E connects to its DirectFlash Shelves (DFS) using 25Gb Ethernet (RoCE) .

The FlashArray//E is the "Capacity Optimized" member of the FlashArray family, designed to replace spinning disk repositories with all-flash efficiency. While the high-performance FlashArray//XL utilizes 100GbE for its backend NVMe-oF connectivity to maximize throughput for mission-critical databases, the //E prioritizes cost-efficiency, density, and power consumption.

Architecture: To maintain this efficiency balance, the backend connectivity for expansion shelves on the //E platform is standardized on 25GbE . This provides ample bandwidth for the QLC-based workloads (typically unstructured data, repository, or Tier 2 block) without the higher cost and power draw of 100GbE optics and controllers.

Comparison: Option A (40G) is a legacy QSFP standard not used in modern Pure backend designs. Option C (100G) is reserved for the performance-tier //XL and high-end //X models.

When unpacking and installing a new Pure Storage FlashArray controller, the initial configuration—such as assigning management IP addresses, subnet masks, and gateways via the puresetup utility—must be done completely out-of-band. Because the array does not yet have an IP presence on the customer's network, the Implementation Engineer must connect directly to the controller's serial console port using a standard serial-to-USB adapter and terminal emulation software (such as PuTTY, SecureCRT, or Tera Term).

To successfully establish a readable CLI session with the custom Linux microkernel running on the FlashArray controllers, the terminal emulator must be configured with the exact serial communication parameters expected by the array. According to Pure Storage hardware documentation, the mandatory COM port settings are:

Baud Rate (Speed): 115,200

Data Bits: 8

Parity: None (N)

Stop Bits: 1

Flow Control: None

This configuration is universally abbreviated as 115200 8-N-1 . If an engineer attempts to use older standard speeds (like 9600 or 38400 baud) or leaves flow control (like Xon/Xoff or RTS/CTS) enabled, the terminal window will display unreadable, garbled characters (often referred to as "wingdings"), or the keyboard inputs will fail to register entirely, preventing the initialization of the array.

On a FlashArray//XR2 or //XR3 controller equipped with an optional Ethernet Mezzanine (EMEZZ) card, the additional ports are enumerated as ETH6, ETH7, ETH8, and ETH9 .

The port numbering logic on these controllers follows a strict sequence:

ETH0 and ETH1: Fixed onboard 1GbE Management ports.

ETH2 and ETH3: Fixed onboard 10/25GbE ports (often used for replication or iSCSI).

ETH4 and ETH5: Reserved or used by the first PCIe slot expansion (if populated with Ethernet).

ETH6 through ETH9: Assigned to the Ethernet Mezzanine (EMEZZ) slot.

The EMEZZ is a specific internal slot distinct from the standard PCIe risers. When populated, the Purity operating system reserves the eth6–eth9 block for these interfaces. Options B and C are incorrect because they describe port ranges that would typically be assigned to PCIe expansion cards in Slot 1 or Slot 2 (e.g., eth10+), or they simply do not align with the hardcoded enumeration logic of the R2/R3 controller architecture. Correct identification of these interfaces is critical for configuring link aggregation (LACP) or assigning iSCSI IPs during the initial setup.

For a Pure Storage FlashArray to fully utilize its predictive support capabilities, it must maintain a persistent, secure outbound connection to the Pure1 cloud infrastructure. This allows the array's Callhome Connection Manager (CCM) to transmit telemetry data, hardware alerts, and heartbeat signals. However, in many enterprise environments, storage management networks do not have direct, unfiltered access to the public internet. Instead, all outbound HTTP/HTTPS traffic must be routed through a corporate proxy server.

To facilitate this, the Implementation Engineer must configure the FlashArray to tunnel its Call Home traffic through the customer's proxy. The officially supported Purity CLI command to achieve this is purearray setattr --proxy https:// < proxy_address > : < port > .

By executing this command, the system modifies its global network attributes. Purity immediately updates the internal routing daemon, instructing it to encapsulate all outgoing Pure1 management traffic and direct it to the specified proxy IP or hostname on the designated port (e.g., port 8080 or 3128). Options B, C, and D are fabricated commands that do not exist within the Purity CLI framework. Once the proxy is set, the engineer should always validate the configuration by running purearray test phonehome to ensure the proxy is properly allowing the traffic to pass through to the Pure Storage cloud endpoints.

DirectFlash Shelves (DFS) connect to the FlashArray controllers using high-speed protocols (typically RoCE - RDMA over Converged Ethernet) that require high-fidelity signal integrity. Due to the high bandwidth (50Gb or 100Gb speeds) and low latency requirements of the NVMe-oF (NVMe over Fabrics) protocol used for backend connectivity, the physical cabling length is strictly limited.

Pure Storage officially supports a maximum cable length of 3 meters for connecting DirectFlash Shelves to the controller or for daisy-chaining shelves (where supported). Cables longer than 3 meters (such as 5m or 7m) introduce signal attenuation and latency that can destabilize the backend fabric, leading to CRC errors, path flapping, or drive disconnections.

Implementation Engineers must ensure that the rack layout allows the shelves to be placed within this 3-meter radius of the controllers. Typically, shelves are racked immediately above or below the controller chassis to minimize cable run distance. Attempting to span across multiple racks using longer, unsupported cables will result in an unsupported configuration and likely immediate I/O errors.

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In a Non-Disruptive Upgrade (NDU) scenario, the goal is to replace the compute and control logic of the array while preserving the existing data and minimizing hardware waste. When upgrading from a FlashArray//X70R2 to an //X70R4, the primary components that change are the Controllers themselves. The chassis, power supplies, and NVRAM modules (depending on the specific generation jump and health) can often be reused or are not the primary target of the replacement in a standard NDU kit.

If a complete array is shipped by mistake (often called a "greenfield" or "net-new" array shipment) instead of the specific upgrade kit, the engineer should only extract and use the Controllers from the new shipment. The existing chassis and its passive components (like the midplane and power supplies) are already racked, cabled, and functioning. Swapping the chassis or power supplies would turn the operation into a disruptive migration or a much more complex "chassis replacement" procedure, which is unnecessary for a controller upgrade.

Therefore, the engineer should unpack the new controllers, perform the NDU procedure to replace the old controllers one by one, and leave the rest of the new hardware (chassis, empty slots, etc.) as spare or return it. This approach adheres to the NDU procedure of swapping the "brains" of the storage while keeping the "body" (chassis and drives) intact.

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When performing a specific legacy upgrade from a FlashArray FA-405 to a FlashArray//X Series , the 2-Port InfiniBand card must be installed in PCIe Slot 3 of the target controller (CT1).

Upgrade Architecture: The legacy FA-400 series utilized InfiniBand (IB) for its high-speed cluster interconnect. The modern FlashArray//X series utilizes PCIe/NTB over an internal midplane or different interconnects. However, during a non-disruptive upgrade (NDU) or data migration where the new //X controller is temporarily clustered with the old FA-405 controller to transfer state and data, they must share a compatible link.

Slot Reservation: The FlashArray//X hardware guide and upgrade procedures strictly designate Slot 3 (the top slot on the riser in many //X chassis configurations) as the reserved location for this temporary InfiniBand interconnect card. Installing it in Slot 0 or 2 would conflict with the primary Host I/O or backend connectivity paths, potentially causing the controller to fail the upgrade pre-checks or preventing the cluster from forming.

FlashArray File Services (FA File) brings unified block and file storage capabilities directly into the Purity operating system, allowing customers to provision high-performance SMB and NFS shares alongside their traditional Fibre Channel and iSCSI volumes.

Once the initial FA File networking (Virtual Interfaces) and DNS/Active Directory integrations are configured, the Implementation Engineer must actually create the file structures for the customer. In the Pure Storage Purity GUI, the logical hierarchy for file storage requires the administrator to first create a "File System," which acts as the top-level container, and then create "Directories" within it that will be exported to clients.

To manage, create, or modify these directories, the Implementation Engineer must navigate through the left-hand navigation pane to Storage > File Systems . Clicking into a specific File System reveals the "Directories" tab. From this central pane, the engineer can create new managed directories, apply specific export policies (defining which IPs or users have read/write access), and configure directory-level snapshot schedules. Option B (Settings > Access > Directory Services) is a common distractor, but that menu path is used exclusively for configuring the array's connection to Active Directory or LDAP for administrative login authentication, not for managing storage directories.

When dealing with power architecture on high-end arrays like the FlashArray//X90 R4, understanding the difference between the base chassis and the expansion shelves is critical. The base //X90 chassis—housing the powerful Intel CPUs, massive memory footprint, and primary PCIe lanes—draws significant wattage and strictly requires 200V-240V (208V minimum) power inputs to function. It will literally not power on if plugged into a 120V circuit.

However, a DirectFlash Shelf (DFS) is merely an external NVMe-oF expansion enclosure. It houses the DirectFlash Modules (DFMs) and the necessary backend I/O modules, but completely lacks the compute-heavy controllers of the main array. Because its overall power draw is significantly lower, the official Pure Storage hardware specifications state that DirectFlash Shelves are fully rated and completely supported to run on standard 120 VAC power indefinitely.

Therefore, the Implementation Engineer can confidently cable the DFS power supplies into the available 120V PDU connections without sacrificing any performance, redundancy, or hardware lifespan. It is a fully supported, permanent configuration.

When adding external capacity to a Pure Storage FlashArray via a DirectFlash Shelf (DFS), Implementation Engineers must adhere to strict, high-speed networking port assignments to ensure maximum backend throughput. Unlike older Fibre Channel or basic SAS expansion shelves that use dedicated SAS cabling, a modern DFS relies on massive 50GbE or 100GbE bandwidth using the NVMe-oF (RDMA over Converged Ethernet - RoCE) protocol to maintain NVMe-level speeds across the external fabric.

According to the official FlashArray//XR4 Port Usage and Definitions hardware matrix, the onboard 100GbE RoCE ports explicitly dedicated to the first loop of a DirectFlash Shelf are physically located on the controllers and identified within the Purity operating system as ETH 18 and ETH 19 .

These specific ports are hardware-optimized to handle the extreme backend IOPS generated by the external DirectFlash Modules communicating back to the primary chassis. Utilizing standard 1GbE/10GbE management/replication ports (such as ETH 0/1) or other generic PCIe Ethernet host interfaces (such as ETH 10/11) is unsupported for the primary DFS backend loop. Plugging the shelf into the wrong ports will result in cabling validation failures during the hardware_check.py execution, preventing the new capacity from being recognized by the array.