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Free ARM EN0-001 Practice Exam with Questions & Answers

Questions 1

Which of the following is an advantage of the single-step debug technique?

Options:
A.

It allows a complete trace of real-time program execution to be captured

B.

It reduces the number of pins required to connect the debugger to the processor

C.

It allows examination of the system state before and after execution of a statement

D.

It requires only one change to the program source code

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Questions 2

As part of the ABI specification, the AAPCS defines which of the following?

Options:
A.

How many levels of nested function calls are permitted on ARM systems

B.

How to measure the maximum amount of stack required by an application

C.

On which mode's stack you need to save the return address in a non-leaf function

D.

Which registers need to be preserved by a function

Questions 3

Using a lower optimization level when compiling will:

Options:
A.

Produce faster code.

B.

Produce smaller code.

C.

Produce non standard-compliant code.

D.

Produce code that might be easier to debug.

Questions 4

When applied to locations in memory configured using a write-back cache strategy, what does a data cache 'clean' operation do?

Options:
A.

Writes dirty data cache lines to memory

B.

Reloads dirty data cache lines from memory

C.

Speculatively preloads data into the cache

D.

Writes dirty data cache lines to memory and marks those lines as invalid

Questions 5

When developing a product using the standard ARM C library, what is the minimum effort required to re-target all platform-specific functions in the library?

Options:
A.

Replace all functions which use semi-hosting

B.

Locate the stack in an area of RAM

C.

Set the locale variable appropriately

D.

All functions in the standard library must be rewritten

Questions 6

In the Generic Interrupt Controller (GIC), when an interrupt is requested, but is not yet being handled, it is in which of the following states?

Options:
A.

Inactive

B.

Active

C.

Pending

D.

Edge-triggered

Questions 7

Consider the following code sequence, executing on a processor which implements ARM Architecture v7-A.

LDR r0, [r1]

STR r0, [r2]

STR r3, [r3]

R1 points to a location in normal memory. R2 and R3 point to device memory.

Which of the following statements best describes the ordering rules which apply to this sequence?

Options:
A.

The two writes to device memory will happen in program order, but the read can be performed out of order

B.

The memory accesses can happen in any order

C.

The memory accesses will happen in program order

D.

The read to r0 and the write from r0 will happen in program order, but the write from r3 can be performed out of order

Questions 8

Which privileged mode can kernel code use to get direct access to the User mode registers R13 and R14?

Options:
A.

Abort mode

B.

System mode

C.

Hypeivisor mode

D.

Supervisor mode

Questions 9

In a multi-processor system, there are four processors numbered 0, 1, 2 and 3. The state of the processors is as follows:

  • CPU 0 and 1 are sleeping in low-power state following a WFI instruction. . CPU 2 is executing program code.
  • CPU 3 is sleeping in low-power state following a WFE instruction.

CPU 2 executes a SEV instruction. What is the effect on the system?

Options:
A.

CPU 0: executing, CPU 1: executing, CPU 2: executing. CPU 3: executing

B.

CPU 0: executing, CPU 1: executing. CPU 2: executing. CPU 3: sleeping

C.

CPU 0: sleeping, CPU 1: sleeping. CPU 2: executing. CPU 3: executing

D.

CPU 0: sleeping, CPU 1: sleeping. CPU 2: sleeping, CPU 3: executing

Questions 10

Which is the best power saving mode to use while waiting to obtain a lock on a semaphore?

Options:
A.

Dormant

B.

Standby

C.

Shutdown

D.

Deep sleep

Exam Code: EN0-001
Certification Provider: ARM
Exam Name: ARM Accredited Engineer
Last Update: Jun 19, 2025
Questions: 210
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