When applied to locations in memory configured using a write-back cache strategy, what does a data cache 'clean' operation do?
When developing a product using the standard ARM C library, what is the minimum effort required to re-target all platform-specific functions in the library?
In the Generic Interrupt Controller (GIC), when an interrupt is requested, but is not yet being handled, it is in which of the following states?
Consider the following code sequence, executing on a processor which implements ARM Architecture v7-A.
LDR r0, [r1]
STR r0, [r2]
STR r3, [r3]
R1 points to a location in normal memory. R2 and R3 point to device memory.
Which of the following statements best describes the ordering rules which apply to this sequence?
Which privileged mode can kernel code use to get direct access to the User mode registers R13 and R14?
In a multi-processor system, there are four processors numbered 0, 1, 2 and 3. The state of the processors is as follows:
CPU 2 executes a SEV instruction. What is the effect on the system?
Which is the best power saving mode to use while waiting to obtain a lock on a semaphore?
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