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Get Certified: Proven Methods to Pass the ARM EN0-001 Exam

Questions 51

The disassembly of a program written in C shows calls to the function__aeabi_fadd. Which one of these compiler floating point options could have been used?

Options:

A.

Hard floating-point linkage

B.

Soft floating-point linkage without floating-point hardware

C.

Hard floating-point linkage with optimization for space

D.

Soft floating-point linkage with floating-point hardware

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Questions 52

Optimizing for space will:

Options:

A.

Produce an image which is decompressed at run-time.

B.

Cause the compiler to unroll loops where possible.

C.

Result in more functions being inlined by the compiler.

D.

Produce smaller code, even if this results in slower execution.

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Questions 53

Assume a little-endian system.

What is the value of R5 after the execution of the following piece of code?

EN0-001 Question 53

Options:

A.

0xBB

B.

0xAABBCC22

C.

0x102

D.

0xCC

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Questions 54

The instruction LDR pc, [ r1 ] takes longer to execute on a particular system, than the instruction LDR r0, [ r1 ]. In both cases, r1 points to the same address in external memory.

Which of the following is the most likely explanation of why it takes more cycles?

Options:

A.

The value read from address r1 must be passed from the data side of the processor to the instruction side

B.

The LDR pc, [r1] causes the instruction pipeline to be flushed, but the LDR r0, [r1] does not

C.

The LDR pc, [ r1 ] instruction requires additional alignment checking, as the result must be half word-aligned (Thumb) or word-aligned (ARM)

D.

The LDR r0, [r1] can be speculatively executed, but the LDR pc, [r1] instruction cannot be speculatively executed

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Questions 55

In the ARM instruction set what is the maximum branch distance for a Branch or Branch and Link instruction?

Options:

A.

±32MB

B.

±4MB

C.

±12KB

D.

±4KB

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Questions 56

In which TWO of the following locations would a compiler typically place local variables? (Choose two)

Options:

A.

ROM

B.

Heap

C.

Cache

D.

Registers

E.

Stack

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Questions 57

The automatic removal of a cache line from a cache to free the location is known as cache line:

Options:

A.

Coherency

B.

Pre-fetch

C.

Eviction

D.

Allocation

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Questions 58

In a loop termination test, how might a programmer indicate to the compiler that the loop iteration count limit is divisible by four?

Options:

A.

AND the count limit with -0x3

B.

Add 4 to the count limit

C.

Subtract 4 from the count limit

D.

Shift the count limit left two bit positions

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Questions 59

What is the maximum value of the immediate field in an ARM SVC instruction?

Options:

A.

0x0

B.

0xF

C.

0xFF

D.

0xFFFFFF

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Questions 60

Consider the following instruction sequence:

STR r0, [r2] ; instruction A

DSB

ADD r0, r1, r2 ; instruction B

LDR r3, [r4] ; instruction C

SUB r5, r6, #3 ; instruction D

At what point will execution pause until the STR access is complete?

Options:

A.

After instruction A and before the DSB

B.

After the DSB and before instruction B

C.

After instruction B and before instruction C

D.

After instruction C and before instruction D

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Exam Code: EN0-001
Exam Name: ARM Accredited Engineer
Last Update: Jun 24, 2024
Questions: 210

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