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Get Certified: Proven Methods to Pass the ARM EN0-001 Exam

Questions 31

Under which of the following data-sharing scenarios would cache maintenance operations be necessary?

Options:

A.

Sharing data with another thread running on the same core

B.

Sharing data with another process running on the same core

C.

Sharing data with an external device

D.

Sharing data with another CPU in an SMP system

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Questions 32

In Architecture ARMv7-A which one of the following has a known physical address at power-on reset?

Options:

A.

The exception vector table

B.

The Memory Management Unit (MMU) translation table

C.

The Stack Pointer (SP)

D.

The System Control Register (SCTLR)

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Questions 33

In an MPCore system, when one core is waiting for resources to be released, what instruction could be used to reduce that core's power consumption?

Options:

A.

WFE

B.

PLD

C.

NOP

D.

DSB

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Questions 34

A Programmer's View CPU model usually provides:

Options:

A.

Cycle-accurate simulation of the CPU.

B.

Instruction-accurate simulation of the CPU.

C.

Simulation of user-defined memory-mapped peripherals.

D.

Cycle-accurate simulation of the cache and memory system.

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Questions 35

Under which of the following circumstances would a DSB instruction be used?

Options:

A.

In a multi-threaded system, when two threads need to be synchronized at a particular point

B.

When accessing a peripheral, it is necessary to halt until the memory access is complete

C.

When it is necessary to temporarily disable interrupts while carrying out a particular memory access

D.

In a multiprocessor system, when it is necessary to halt one of the cores while the other completes a critical task

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Questions 36

In the CPSR, 1=0 and F=1. Which of the following is TRUE in this case?

Options:

A.

Both IRQs and FIQs are enabled

B.

Both IRQs and FIQs are disabled

C.

IRQs are disabled and FIQs are enabled

D.

IRQs are enabled and FIQs are disabled

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Questions 37

Which one of the following debug methods is the least intrusive for analyzing a timing related bug?

Options:

A.

Place breakpoints on strategic locations to locate the problem area

B.

Instrument the code with print statements to locate the problem area

C.

Use debug hardware to place watchpoints on strategic data memory locations

D.

Use trace hardware to capture a trace log up to the point of the crash

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Questions 38

Which of the following ARM processors has the best energy efficiency (measured in mW/MHz)?

Options:

A.

Cortex-M0+

B.

Cortex-M4

C.

Cortex-R4

D.

Cortex-A15

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Questions 39

Literal pool loads to access constants at run-time can be minimized by:

Options:

A.

Ensuring constants can be encoded as immediates in the current instruction set.

B.

Storing the code in ROM.

C.

Using Thumb code rather than ARM code.

D.

Compiling and linking as position-independent code.

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Questions 40

It is common to declare structures as "packed" in order to minimize data memory size. Which of the following accurately describes the effect of this?

Options:

A.

Members will be stored as bit-fields

B.

Data Aborts will be disabled for all structure accesses

C.

Structure members will be re-ordered so that the smallest are first

D.

Multi-byte members are not required to be naturally aligned

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Exam Code: EN0-001
Exam Name: ARM Accredited Engineer
Last Update: Jun 23, 2024
Questions: 210

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