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Get Certified: Proven Methods to Pass the ARM EN0-001 Exam

Questions 11

Which one of the following features must any processor support to conform to the ARMv7-A architecture?

Options:
A.

NEON (Advanced SIMD)

B.

Thumb-2 technology

C.

TrustZone (Security Extensions)

D.

Generic Interrupt Controller

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Questions 12

Which of the following operations would count as intrusive to normal processor operation?

Options:
A.

Tracing using Embedded Trace Macrocell (ETM)

B.

Halt mode debugging

C.

Monitor mode debugging

D.

Using the Performance Monitor Unit

Questions 13

A 32KB 4-way set associative instruction cache supports a cache line size of 64 bytes. How many bits are required to index a cache line in a way?

Options:
A.

6 bits

B.

7 bits

C.

9 bits

D.

15 bits

Questions 14

Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.

How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?

Options:
A.

5 cycles

B.

7 cycles

C.

8 cycles

D.

15 cycles

Questions 15

The Performance Monitoring Unit (PMU) of a Cortex-A9 processor permits direct measurement of which one of the following?

Options:
A.

Cache Size

B.

Clock Speed

C.

Program size

D.

Numbers of instructions executed

Questions 16

In an ARMv7-R processor, with which level of the memory system is the Memory Protection Unit (MPU) associated?

Options:
A.

Level 1

B.

Level 2

C.

Level 3

D.

Level 4

Questions 17

When an ARMv7-A MPCore system is in SMP mode, which of the following TWO operations can the processor handle automatically? (Choose two)

Options:
A.

Coherency management between all L1 data caches

B.

Broadcast of some inner-shared cache and TLB maintenance operations

C.

Broadcast of some outer-shared cache and TLB maintenance operations

D.

Coherency management between all L1 instruction caches

E.

Coherency management between all external caches

Questions 18

What will be the contents of R2 after the execution of the following piece of code?

LDRR1, =0xAABBCCDD

MOV R2, #0x4

ANDSR1, R1, #0x4

ADDNE R2, R2, #0x4

Options:
A.

R2 = 0x4

B.

R2 = 0x8

C.

R2 = 0xAABBCCDD

D.

R2 = 0xAABBCCD4

Questions 19

Assuming a 4-core Cortex-A9 SMP system which does not use the Accelerator Coherency Port (ACP). and operates the L1 caches in writeback mode, in which of the following situations is a cache clean operation required?

Options:
A.

An external DMA engine modifies data in a region of data memory which is already cached by the processor

B.

An external agent needs to read data which has been modified by the processor in a cacheable memory region

C.

Debugger reads data from a shared, cacheable memory location

D.

One core modifies data in a shared cacheable memory region

Questions 20

What side-effect could using a debugger to read memory contents have?

Options:
A.

The memory contents could be set to zero

B.

Some memory contents could be rewritten

C.

The processor MMU pagetables could be modified

D.

The processor cache could be cleaned or/and invalidated

Exam Code: EN0-001
Certification Provider: ARM
Exam Name: ARM Accredited Engineer
Last Update: Jan 24, 2025
Questions: 210
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