Get Certified: Proven Methods to Pass the ARM EN0-001 Exam

Which one of the following features must any processor support to conform to the ARMv7-A architecture?

Which of the following operations would count as intrusive to normal processor operation?

A 32KB 4-way set associative instruction cache supports a cache line size of 64 bytes. How many bits are required to index a cache line in a way?

Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.

How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?

The Performance Monitoring Unit (PMU) of a Cortex-A9 processor permits direct measurement of which one of the following?

In an ARMv7-R processor, with which level of the memory system is the Memory Protection Unit (MPU) associated?

When an ARMv7-A MPCore system is in SMP mode, which of the following TWO operations can the processor handle automatically? (Choose two)

What will be the contents of R2 after the execution of the following piece of code?

LDRR1, =0xAABBCCDD

MOV R2, #0x4

ANDSR1, R1, #0x4

ADDNE R2, R2, #0x4

Assuming a 4-core Cortex-A9 SMP system which does not use the Accelerator Coherency Port (ACP). and operates the L1 caches in writeback mode, in which of the following situations is a cache clean operation required?

What side-effect could using a debugger to read memory contents have?